1. Field of the Invention
The present invention relates to non-volatile memory (NVM) cells and, more particularly, to an NVM cell with a heating element.
2. Description of the Related Art
A non-volatile memory is a semiconductor memory that retains data stored in the memory after power to the memory has been removed. Three well-known non-volatile memories include electrically programmable read-only-memories (EPROMS), electrically erasable programmable read-only-memories (EEPROMS), and flash EPROMS.
The three types of memories are similar in structure (with each memory having an MOS-type structure that utilizes a floating gate and a control gate in lieu of a single conventional gate), but differ in the way the memories are programmed and erased. EPROMS are programmed by a process known as hot electron injection, and are erased by exposure to ultraviolet (UV) light. EEPROMS are programmed and erased electrically by a process known as Fowler-Nordheim tunneling. Flash EPROMS, in turn, are a combination, being programmed by hot electron injection, and erased by Fowler-Nordheim tunneling.
One well-known type of EEPROM is a floating-gate tunneling-oxide (FLOTOX) EEPROM. FIGS. 1A-1C show views that illustrate a prior-art FLOTOX EEPROM cell 100. FIG. 1A shows a plan view, while FIGS. 1B and 1C show cross-sectional views taken along lines 1B-1B and 1C-1C, respectively, in FIG. 1A.
As shown in FIGS. 1A-1C, FLOTOX EEPROM cell 100 includes an EEPROM 102 which retains data, and an access transistor 104 which controls access to EEPROM 102. (Whenever two or more EEPROMS share a common drain line and are separately erasable, each EEPROM requires an access transistor due to the high drain voltages that are used during erase.)
In addition, FLOTOX EEPROM cell 100, which utilizes a conventionally-formed, p-single-crystal silicon semiconductor material 110, further includes spaced-apart n-type doped regions 112, 114, and 116 that are formed in p-semiconductor material 110. As shown, the doped regions 112, 114, and 116 each have a heavily-doped region (N+) and a lightly-doped region (N−).
Doped regions 112 and 114 form the source and drain regions of EEPROM 102, while doped regions 114 and 116 form the source and drain regions of access transistor 104. Thus, doped region 114 is a shared region which functions as the drain of EEPROM 102 and the source of access transistor 104.
Further, FLOTOX EEPROM cell 100 also includes a first channel region 120 of p-semiconductor material 110 that lies between and contacts doped regions 112 and 114, and a second channel region 122 of p-semiconductor material 110 that lies between and contacts doped regions 114 and 116.
FLOTOX EEPROM cell 100 additionally includes a first gate isolation region 124 that contacts the top surface of p-semiconductor material 110 over first channel region 120, and a second gate isolation region 126 that contacts the top surface of p-semiconductor material 110 over second channel region 122. Cell 100 also includes a tunnel window 130 in first gate isolation region 124 that exposes a portion of doped region 114, and a thin tunnel oxide region 132 that contacts doped region 114 in tunnel window 130.
As further shown in FIGS. 1A-1C, FLOTOX EEPROM cell 100 includes a floating gate 140 that contacts first gate isolation region 124 and tunnel oxide region 132, and an interpoly dielectric 142 (e.g., oxide-nitride-oxide) that contacts floating gate 140. Cell 100 also includes an edge oxide 144 that contacts opposing side walls of floating gate 140, and a control gate 146 that contacts interpoly dielectric 142. Thus, floating gate 140 lies over and is insulated from first channel region 120, and control gate 146 lies over and is insulated from floating gate 140. Cell 100 additionally includes an access gate 150 that lies over and is insulated from second channel region 122 by second gate isolation region 126, and non-conductive side wall spacers 152.
In operation, cell 100 is programmed by applying a program voltage, such as +12V, to control gate 146 and an access voltage, such as +3.3V, to access gate 150 while grounding doped region 116 and floating doped region 112. Under these bias conditions, electrons from doped region 114 tunnel through tunnel oxide region 132 by way of the Fowler-Nordheim tunneling mechanism, and begin accumulating on floating gate 140 where the increased negative charge raises the threshold voltage of the cell.
Cell 100 is erased by applying the access voltage to access gate 150 and an erase voltage, such as +12V, to doped region 116 while grounding control gate 146 and floating doped region 112. Under these bias conditions, electrons from floating gate 140 tunnel back through tunnel oxide region 132 to doped region 114 where the reduced negative charge on floating gate 140 lowers the threshold voltage of the cell. (The thickness of first gate isolation region 124 and the magnitudes of the program and erase voltages are selected so that Fowler-Nordheim tunneling does not occur through first gate isolation region 124.)
Once programmed or erased, cell 100 is read by applying a first read voltage, such as +3.3V, to control gate 146, the access voltage to access gate 150, and a second read voltage, such as +3.3V, to doped region 116 while grounding doped region 112. When cell 100 is erased, a large current flows from doped region 116 to doped region 114 to doped region 112 due to the lower threshold voltage of an erased cell, while a much smaller current or no current at all flows from doped region 116 to doped region 114 to doped region 112 when cell 100 is programmed due to the higher threshold voltage of a programmed cell.
FIGS. 2A-2C show views that illustrate a prior-art flash EPROM 200. FIG. 2A shows a plan view, while FIGS. 2B and 2C show cross-sectional views taken along lines 2B-2B and 2C-2C, respectively, in FIG. 2A. As shown in FIGS. 2A-2C, flash EPROM 200, which utilizes a conventionally-formed, p-single-crystal silicon semiconductor material 210, includes spaced-apart n-type doped regions 212 and 214 that are formed in p-semiconductor material 210. As shown, doped region 212, which functions as the source region, has a heavily-doped region (N+) and a lightly-doped region (N−), while doped region 214, which functions as the drain region, has a heavily-doped region (N+).
Further, flash EPROM 200 also includes a channel region 216 of p-semiconductor material 210 that lies between and contacts doped regions 212 and 214, and a gate dielectric 220 that contacts the top surface of p-semiconductor material 210 over channel region 216. In flash EPROM 200, the thickness of gate dielectric 220 is comparable to the thickness of thin tunnel oxide region 132.
As further shown in FIGS. 2A-2C, flash EPROM 200 includes a floating gate 222 that contacts gate dielectric 220, and an interpoly dielectric 224 (e.g., oxide-nitride-oxide) that contacts floating gate 222. Flash EPROM 200 also includes an edge oxide 228 that contacts opposing side walls of floating gate 222, and a control gate 230 that contacts interpoly dielectric 224. Floating gate 222 lies over and is insulated from channel region 216, and control gate 230 lies over and is insulated from floating gate 222. Flash EPROM 200 additionally includes non-conductive side wall spacers 232.
In operation, flash EPROM 200 is programmed by applying a programming voltage to control gate 230, a drain voltage to drain region 214, and ground to source region 212. The programming voltage applied to control gate 230 induces a positive potential on floating gate 222 which, in turn, attracts electrons to the surface of channel region 216 to form a channel 234.
In addition, the source-to-drain voltage sets up an electric field which causes electrons to flow from source region 212 to drain region 214 via channel 234. As the electrons flow to drain region 214, the electric field, which has a maximum near drain region 214, accelerates these electrons into having ionizing collisions that form channel hot electrons near drain region 214.
A small percentage of the channel hot electrons are then injected onto floating gate 222 via gate dielectric 220. Flash EPROM 200 is programmed when the number of electrons injected onto floating gate 222 is sufficient to prevent channel 234 from being formed when a read voltage is subsequently applied to control gate 230.
Flash EPROM 200 is erased by applying an erase voltage, such as +12V, to doped region 212 while grounding control gate 230 and floating doped region 214. The graded N+/N− junction of doped region 212 prevents junction breakdown. Under these bias conditions, electrons from floating gate 222 tunnel through gate dielectric 220 to doped region 212 where the reduced negative charge on floating gate 222 lowers the threshold voltage of EPROM 200.
In a flash EPROM array, because flash EPROMS do not utilize an access transistor, all of the flash EPROMS in the array are electrically erased at the same time in a single operation. (Large arrays can be broken into subarrays with select transistors where all of the flash EPROMS in the subarray are erased at the same time.) Thus, flash EPROMS are much smaller than EEPROM cells (one transistor versus two transistors), but can not be individually erased without access transistors.
Once programmed or erased, flash EPROM 200 is read by applying a first read voltage, such as +3.3V, to control gate 230, and a second read voltage, such as +3.3V, to doped region 214 while grounding doped region 212. When flash EPROM 200 is erased, a large current flows from doped region 214 to doped region 212 due to the lower threshold voltage of an erased flash EPROM, while a much smaller current or no current at all flows from doped region 214 to doped region 212 when flash EPROM 200 is programmed due to the higher threshold voltage of a programmed flash EPROM.
One problem with EEPROM cell 100 and flash EPROM 200 is that EEPROM cell 100 and flash EPROM 200 can only be programmed and erased a limited number of times before failing. The movement of electrons back and forth through tunnel oxide region 132 and gate dielectric 220 while programming and erasing damages the thin oxide and leads to the formation of traps which, in turn, provide a leakage path for the charge stored on the floating gate.
For example, current-generation EEPROM cells typically provide 1,000,000 erase-program cycles before failure, while current-generation flash EPROMS typically provide 10,000 erase-program cycles. Flash EPROMS tend to wear out quicker than EEPROM cells because only select cells need be erased in an EEPROM array, whereas all of the EPROMS in a flash array (or subarray) are erased during each erase cycle.
Although these numbers of erase-program cycles are sufficient for many applications, there is a need for a non-volatile memory that provides a substantially larger number of erase-program cycles.